In addition to there being many different numerical systems, such as binary systems, base eight systems, decimal systems, etc, there are often different ways of counting within those systems. In a binary based system, a digit of a particular number is either represented by a “1” or a “0”. When such systems are used for counting, the values of the digits are changed. For example, when counting in a binary system, the binary number “0010” becomes “0011” when the number is incremented. However, conventional counting in a binary system also provides for the use of a “carry” number. That is, when a value in a binary system is incremented, a bit having a “1” may be changed to a “0” and a “1” is added to the next most significant bit. For example, when incrementing a count of the binary value “0111”, the resulting value will be “1000”. A “1” is carried in each of the first three bits and added to the adjacent more significant bit. Such counting using a carry number can lead to the changing of may bits. As can be seen in the example above, all four bits are changed. Such changing of bits can have a negative impact on the performance of a electronic circuit implementing a counter by having greater complexity, slower speed, increased power consumption, etc.
Efforts have been made to provide simpler counting systems based upon binary. A single bit transition counter, such as a Grey Code Counter was developed. A Grey Code represents each number in a sequence of intergers as a binary string of the length N in an order such that adjacent integers have Grey Code representations that differ in only one bit position; Incrementing a value in a Grey Code sequence therefore requires the changing of just one bit at a time. Grey Code Counters are often implemented using a state machine, and therefore explicitly require that every unique state be defined. In products that do not have single level wide logic decode capabilities, such as an FPGA, the Grey counter has been implemented using XOR gates between intermediate stages. Devices such as CPLDs have wide single level logic which can be used to decode the intermediate stages quickly, with identical delay times between stages. With larger Grey Code Counters, this can be quite a burden, requiring a prohibitively detailed description of a state machine, which is prone to data entry errors. For example, a 16 bit Grey Code Counter contains 216 states, or 65536 states. Also, subsequent software compilation, as fitting for PLDs or ASICs, can also be quite demanding where the fitter may never reach a conclusion, and if so may be logically inefficient.
Accordingly, there is a need for an improved integrated circuit and method of implementing a counter in an integrated circuit.
There is also a need for a counter for use in integrated circuits having reduced power consumption compared to conventional devices.
There is a further need for a counter which can be implemented in software compilers having reduce fit/compile times.